The present invention relates generally to semiconductor memory devices, and in particular, the present invention relates to flash cell (floating-gate memory cell) fuse circuits, their applications and their operation.
Electronic information handling or computer systems, whether large machines, microcomputers or small and simple digital processing devices, require memory for storing data and program instructions. Various memory systems have been developed over the years to address the evolving needs of information handling systems. One such memory system includes semiconductor memory devices.
Semiconductor memory devices are rapidly-accessible memory devices. In a semiconductor memory device, the time required for storing and retrieving information generally is independent of the physical location of the information within the memory device. Semiconductor memory devices typically store information in a large array of cells.
Computer, communication and industrial applications are driving the demand for memory devices in a variety of electronic systems. One important form of semiconductor memory device includes a non-volatile memory made up of floating-gate memory cells called flash memory. Flash memory is often used where regular access to the data stored in the memory device is desired, but where such data is seldom changed. Computer applications use flash memory to store BIOS firmware. Peripheral devices such as printers store fonts and forms on flash memory. Digital cellular and wireless applications consume large quantities of flash memory and are continually pushing for lower operating voltages and higher densities. Portable applications such as digital cameras, audio recorders, personal digital assistants (PDAs) and test equipment also use flash memory as a medium to store data.
Conventional flash memory cells make use of a floating-gate transistor including a source region, a drain region, a floating-gate layer and a control-gate layer. In such devices, access operations are carried out by applying biases to each of these terminals. Write operations are generally carried out by channel hot-carrier injection. This process induces a flow of electrons between the source and the drain, and accelerates them toward a floating gate in response to a positive bias applied to the control gate. Erase operations are generally carried out through Fowler-Nordheim tunneling. This process may include electrically floating the drain region, grounding the source region, and applying a high negative voltage to the control gate. Read operations generally include sensing a current between the source and the drain, i.e., the MOSFET current, in response to a bias applied to the control gate. If the memory cell is programmed, its threshold voltage will be near or above the control-gate bias such that the resulting current is low to non-existent. If the memory cell is erased, its threshold voltage is well below the control-gate bias such that the current is substantially higher.
Although attempts have been made to carefully control the fabrication of such memory devices so as to increase their yield, there invariably will be differences in operating characteristics of memory devices fabricated at different times. These differences in operating characteristics are primarily due to processing variations and may even occur between different semiconductor wafers in a single batch of wafers. By way of example, in a flash memory device, the threshold voltage of memory cell of one memory device may change one amount after applying programming biases and a cell of another supposedly identical memory device may change a different amount after applying the same programming biases. In order to accommodate such variations in memory device characteristics, designs may allow for adjustment or trimming of voltages generated by the memory device. By trimming such internally-generated analog voltages, both memory devices can operate using the same supply voltages and the same timing characteristics, thus making their differing operating characteristics transparent to the end user. Fuse banks are often used to store such trimming parameters.
Fuse banks may also find use in device redundancy. Redundancy is the practice of fabricating additional or redundant elements, e.g., a row or column of memory cells that can be activated to replace a defective primary element. During testing, if a defective primary element is identified, its location address may be stored in a fuse bank associated with a redundant element. Addresses received by the memory device are compared to the fuse bank to determine whether access should be directed to a primary element or to the associated redundant element. Other uses of fuse banks include storage of enable bits for specific test configurations.
Fuse banks generally contain banks of non-volatile storage locations. While fuse banks may contain banks of fusible links as their storage elements, they may alternatively contain other non-volatile storage elements such as anti-fuses as well as floating-gate transistors. The state of the individual storage elements, e.g., open circuit or closed circuit in the case of fuses and anti-fuses, and programmed or erased in the case of floating-gate transistors, determines the parameter value stored in a fuse bank.
FIG. 1 is an example of a fuse circuit 100 utilizing floating-gate transistors as non-volatile storage elements. The fuse circuit 100 uses a flip-flop configuration with two floating-gate transistors and may be referred to as a double flash cell. The fuse circuit 100 includes p-channel field-effect transistors (pFETs) 120 and 122 having their sources coupled to a first potential node 124. The first potential node 124 is coupled to receive a first potential, such as a supply potential Vcc. The pFET 120 has its gate coupled to the drain of the pFET 122 at node 138 while the pFET 122 has its gate coupled to the drain of the pFET 120 at node 136. An n-channel field-effect transistor (nFET) 116 has a drain coupled to the drain of the pFET 120, a source coupled to a floating-gate transistor 112 and a gate coupled to control node 134. An nFET 118 has a drain coupled to the drain of the pFET 122, a source coupled to a floating-gate transistor 114 and a gate coupled to control node 134. The floating-gate transistors 112 and 114 each have a source coupled to a second potential node and a gate coupled to control node 132. The second potential node 126 is coupled to receive a second potential lower than the first potential, such as a ground potential Vss. The fuse circuit 100 further includes an inverter 128 having an input coupled to the node 136 and an output coupled to the fuse circuit output 130.
The floating-gate transistor 112 is programmed and the floating-gate transistor 114 is erased to store a first fuse data value while the floating-gate transistor 112 is erased and the floating-gate transistor 114 is programmed to store a second fuse data value. To read the fuse circuit 100, a logic high signal is applied to control nodes 132 and 134, thus activating the nFETs 116 and 118 and activating one of the floating-gate transistors 112 or 114. Applying a logic high signal to control node 134 will couple the floating-gate transistors 112 and 114 between the first potential node 124 and the second potential node 126. Due to the cross-coupled nature of the pFETs 120 and 122, one will latch activated while the other will latch deactivated depending on the data value stored by the floating-gate transistors 112 and 114. For the schematic shown, a logic low data value is presented at the fuse circuit output 130 if the fuse circuit 100 is storing the first data value and a logic high data value is presented at the fuse circuit output 130 if the fuse circuit 100 is storing the second data value. As device operating voltages are reduced, fuse circuits of the type shown in FIG. 1 may become inoperable or may latch too slowly for effective operation.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative fuse circuits for use in memory devices and apparatus making use of such memory devices, as well as methods of their operation.
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
Fuse circuits based on a single flash cell or floating-gate memory cell are adapted for use in memory devices, particularly in low-voltage applications. Such fuse circuits include a floating-gate memory cell for storing a data value and a fuse latch to hold and transfer the data value of the floating-gate memory cell at power-up or upon request. A latch driver circuit can write data values to the fuse latch without affecting the data value stored in the floating-gate memory cell. The ability to write to the fuse latch without affecting the stored data value can be useful in testing of the memory device. The fuse circuits can further utilize the same structure, pitch, bit-line organization and word-line organization as the memory device""s memory array, thus simplifying fabrication and leading to more efficient use of die area. As the fuse circuits can utilize the same structure and organization, the data value of the fuse circuit can be programmed, erased and read using the same data path as the regular memory array.
For one embodiment, the invention provides a fuse circuit. The fuse circuit includes a floating-gate transistor having a first source/drain region, a second source/drain region, and a gate. The fuse circuit further includes a reset transistor having a first source/drain region coupled to a first potential node, a second source/drain region coupled to a latch input node, and a gate coupled to a first control node. The fuse circuit still further includes a set transistor having a first source/drain region coupled to the latch input node, a second source/drain region coupled to the first source/drain region of the floating-gate transistor, and a gate coupled to a second control node. The fuse circuit still further includes a fuse latch having an input coupled to the latch input node and an output coupled to an output node. For a further embodiment, the fuse circuit includes a latch driver circuit capable of setting an output value of the fuse latch without regard to, and without disturbing the data value of, the floating-gate transistor.
For another embodiment, the invention provides a memory device having an array of floating-gate memory cells, each memory cell located at an intersection of a word line and a local bit line. The memory device includes a reset transistor having a first source/drain region coupled to a first potential node, a second source/drain region coupled to a latch input node, and a gate coupled to a first control node. The memory device further includes a set transistor having a first source/drain region coupled to the latch input node, a second source/drain region coupled to a first local bit line, and a gate coupled to a second control node. The memory device still further includes a fuse latch having an input coupled to the latch input node and an output coupled to an output node. For a further embodiment, a first source/drain region of a first floating-gate memory cell is coupled to the first local bit line, a second source/drain region of the first floating-gate memory cell is coupled to a second potential node, and a gate of the first floating-gate memory cell is coupled to a first word line of the memory device. For a still further embodiment, the memory device includes a latch driver circuit coupled to the fuse circuit capable of setting an output value of the fuse latch without regard to, and without disturbing the data value of, the first floating-gate memory cell.
For yet another embodiment, the invention provides a method of operating a memory device. The method includes deactivating a first field-effect transistor having a first source/drain region coupled to a fuse latch input node and a second source/drain region coupled to a local bit line of the memory device, and activating a second field-effect transistor having a first source/drain region coupled to a first potential node and a second source/drain region coupled to the fuse latch input node. The method further includes resetting a fuse latch in response to deactivating the first field-effect transistor and activating the second field-effect transistor, wherein the fuse latch has an input coupled to the fuse latch input node and an output coupled to an output node. For a further embodiment, the method includes deactivating the second field-effect transistor subsequent to resetting the fuse latch. For a still further embodiment, the method includes activating the first field-effect transistor subsequent to deactivating the second field-effect transistor, and driving a word line of a floating-gate memory cell coupled to the local bit line.
For still another embodiment, the invention provides a method of operating a memory device. The method includes generating a first control signal indicative of whether it is desired to set a fuse latch of a first fuse circuit to some fuse data value without regard to a data value of a floating-gate memory cell associated with the first fuse circuit and generating a second control signal indicative of the fuse data value. The method further includes deactivating a first field-effect transistor and a second field-effect transistor when the first control signal has a first logic level, wherein the first field-effect transistor is coupled between a first potential node and an output node of the fuse circuit, and wherein the second field-effect transistor is coupled between a second potential node and the output node of the fuse circuit. The method still further includes selectively activating either the first field-effect transistor or the second field-effect transistor in response to a logic level of the second control signal when the first control signal has a second logic level.
The invention further provides methods and apparatus of varying scope.